BeagleBone Black GPIO Performance: PRU -> 1 memory mapped GPIO
This test was intended to estimate the maximum performance of the GPIO, that is not direct wired to the PRU, using the PRU. The first test was done on the PRU1.
Source Code
#define GPIO2 0x481ac000
#define GPIO_SETDATAOUT 0x194
#define GPIO_CLEARDATAOUT 0x190
#define INS_PER_DELAY_LOOP 2 //two instruction per delay loop
#define DELAY 1 //see the delay number in the title of the test
#define GPIO73 1<<9 //0x200
TOP:
LBCO r0, c4, 4, 4 //load SYSCFG register to r0 (use c4 const addr)
CLR r0, r0, 4 //clear bit 4 (standby init)
SBCO r0, c4, 4, 4 //store the modified r0 back at the load address
//memory assignments
mov r1, GPIO2 | GPIO_SETDATAOUT //load addr for gpio, set data r1
mov r2, GPIO2 | GPIO_CLEARDATAOUT //load addr for gpio to clear data
mov r3, GPIO73 //9th bit, GPIO73
LEDON:
sbbo r3, r1, 0, 4
mov r0, DELAY //store the length of the delay in REG0
DELAYON:
sub r0, r0, 1 //Decerement REG0 by 1
qbne DELAYON, r0, 0 //loop to delay DELAYON, unless REG0=0
LEDOFF:
sbbo r3, r2, 0, 4
mov r0, DELAY
DELAYOFF:
sub r0, r0, 1 //decrement REG0 by 1
qbne DELAYOFF, r0, 0 //loop to delayoff unless reg0=0
jmp LEDON
GPIO frequency 500 kHz, delay in program 100, 0,5 µs TIME/DIV
GPIO frequency 4,55 MHz, delay in program 10, 0,1 µs TIME/DIV
GPIO frequency 8 MHz, delay in program 5, 0,05 µs TIME/DIV
GPIO frequency 9 MHz, delay in program 4, 0,02 µs TIME/DIV
GPIO frequency 11,11 MHz, delay in program 3, 0,02 µs TIME/DIV
GPIO frequency 12,5 MHz, delay in program 2, 0,02 µs TIME/DIV
GPIO frequency 12,5 MHz, delay in program 1, 0,02 µs TIME/DIV
GPIO frequency 12,5 MHz, no delay, 0,02 µs TIME/DIV
All delays were eliminated.
LEDON:
sbbo r3, r1, 0, 4
sbbo r3, r2, 0, 4
jmp LEDON
Is there a difference between the ordinary and PRU-wireable GPIOs?
No, there is no difference. We also tested P8-14 (GPIO_26) with the same program in order to compare the performance of the GPIOs (GPIO73 versus GPIO26). The maximum speed was identical with the PRU-wireable GPIO (~12,5 MHz).