Clock and Expansion Cards 2017-07-04T10:01:39+00:00

Clock Card

Clock Card is designed to generate a single clock 28.8 MHz for all receivers. The use of such an external synchronization unit has the following advantages:

  • Enhanced stability;
  • Reduction of the reference frequency’s 28.8 MHz phase noise;
  • Improvement of the temperature characteristics;
  • Opportunity to choose the required level of the frequency stability (0.1/0.5/1.0/2.0 ppm);
  • Minimization of the delays and clock drift between single receivers using the star-consecutive topology

The clock card includes the following components:

  • TXCO 28.8 MHz
    • Default: 2 PPM initial offset, 0.5-1 PPM temperature drift.
    • Optional: higher precision (0.1/0.5/1.0 ppm) is available on request.
  • Buffer Gate
  • Clock Buffer
  • LPF (cut-off 35 MHz)
  • SMD LED indicators
  • I2C interface
  • I2C 8bit Register
  • Power indication LED (+3.3 V)
  • Ultraminiature Coaxial Connectors

Buffer Gate

TCXO usually has an output resistance of about 10K , which does not allow direct connection of the TCXO to the Clock Buffer input. The Buffer Gate is necessary in order to match the high output impedance of TCXO and low 50 Om input impedance of the Clock Buffer 5PB1104. The simplest solution is to use Dual Schmitt-Trigger Inverter SN74LVC2G14. “The SN74LVC2G14 device is a high drive CMOS device that can be used for a multitude of buffer type functions where the input is slow or noisy. The device can produce 24 mA of drive current at 3.3 V, making it ideal for driving multiple outputs and good for high-speed applications up to 100 MHz” [Source: Datasheet]. The inverters are connected parallel in order to increase the output power.

Clock Buffer

The clock card is based on the high-performance LVCMOS Clock Buffer 5PB1104 produced by Integrated Devices Technology, Inc. The 5PB11xx (Datasheet) is a high-performance LVCMOS Clock Buffer Family. It has best-in-class Additive Phase Jitter of 50fsec RMS. There are five different fan-out variations, 1:2 to 1:10, available. The IDT5PB11xx also supports a synchronous glitch-free Output Enable function to eliminate any potential intermediate incorrect output clock cycles when enabling or disabling outputs. It comes in various packages and can operate from a 1.8V to 3.3V supply.

I2C 8 Bit Register

The Clock Card includes one 8-bit configuration register with LED indicators 1×8. This component enables the expansion of the underlying device (coherent receiver) with the following features:

  • Input antenna switching in the direction finding system
  • Management of the range filter switching in the pre-selectors
  • Calibration and management of the directional antenna locations. Tuning to the necessary bearing.
  • Calibration of the coherent receivers using the noise sources which enable calibration and synchronisation of data streams using the gated RF noise.

Current realization of the Clock Card  integrates the PCA9534 chip that consists of an 8-bit Configuration register (Input or Output selection); 8-bit Input register, 8-bit Output register and an 8-bit Polarity Inversion register (active HIGH or
active LOW operation). The system master can enable the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for each input or output is kept in the corresponding Input or Output register. The usage of the register is described in the support section.

I2C Interface

I2C-bus repeater provides additional possibilities for the management of the peripheral devices based on the I2C-interface, e.g. low-speed DAC/ADC, step motor, sensor information reading (e.g. temperature, ventilator cooling, system control), etc.


In general, the usage of the external clock buffer can lead to additional interference. Synchronization signals, which are square pulses at the 28.8 MHz, create a wide range of signals with harmonics, which are multiples of the 28.8 MHz: 2fs, 3fs, 4fs, 5fs, and can be the source of additional interferences. Therefore, it is necessary to utilise a filter with a nominal cutoff frequency at 29 … 30 MHz for the suppression of higher order harmonics (see section Low Pass Filters 30MHz Cards for more information).

Signal Wave Form EMI Suppression Effect
B A-SignalWaveForm-1 emi-suppression-effect-b
A, C B-Signal-WaveForm-1 emi-suppression-effect-ac

As seen from the table, using LPF with a cut-off frequency of 35 MHz substantially reduces the unwanted harmonics, and hence, reduces the possibility of undesired spurs in the spectrum of the received signal.

Ultraminiature Coaxial Connectors

Ultraminiature Coaxial Connectors are installed on the card in order to distribute the clock frequency on all single receivers using coaxial pigtails. The usage of coaxial pigtails reduces the phase noise and eliminates the interference of the clock frequency, including harmonics, with the received signal.

Example: 2 ppm clock

Example: 0.2 ppm clock

The clock generator and clock expansion cards are not restricted to the 28.8 MHz. Custom builds are possible for other clock frequencies with required precision.

Clock Card supporting 10 MHz Synchronisation

sample of the clock card with configurable clock

Sometimes, it is necessary to use 10 MHz as a reference frequency, e.g. from a GPS receiver. In this case, we propose the usage of a specially modified clock card (CLK_CARD10) that has been adapted to support the external reference frequency 10 MHz. In this card, the TCXO 28.8 MHz is replaced by the I2C Configurable Clock Generator (see figure above).

The I2C Configurable Clock Generator supports two operating modes:

  • synchronisation from an external source, e.g. 10 MHz, GPS
  • synchronisation from an internal source, e.g. standard TCXO 27 MHz, 0.5…1 ppm

The CLK_CARD10 can be used in all models of the coherent receivers.

Expansion Card

The  Expansion Card has the same architecture as the Clock Card but does not include TCXO 28.8 MHz and Buffer Gate.


  1. Kushagra Dixit 18. March 2017 at 16:58 - Reply

    Can I get an exact parts list. I want to build this for a project to capture frequency hopping gsm. As I have a very low budget. My only option is to make one myself.

  2. admin 18. March 2017 at 17:29 - Reply

    we are planning to provide a tutorial how to build the 2 or 3 channel coherent receiver using RTL-SDR v.3 modules without additional components (e.g. clock card). Will it be enough for your project? In case of GSM you can receive the send- and receive-side using only 2 receivers.

    Moreover, why you actually need the coherence in your scenario? If you have several dongles you can provide some kind of the synchronisation backon in order to get the time synchronisation of IQ-streams then you can decode the channel in parallel and after that joint the channels after that. If you don’t have packet losses, raw data stream from the receiver remains synchron.

  3. Kushagra Dixit 4. April 2017 at 20:20 - Reply

    I need to have a 4 channel reciever for my project. it requires around 7 mhz of bandwidth. I want to use them as a single receiver. for which I am comparing and synchronizing the phase in MATLAB but I need to time synchronize them externally. Also what exact buffergate is being used here ? Can I get the PCB design. Or I’ll have to make one myself?

    • igor 6. April 2017 at 10:06 - Reply

      we added a detailed description to the buffer gate section.

  4. Kushagra Dixit 17. April 2017 at 9:01 - Reply

    Thank You

Leave A Comment