16-bit coherent receiver (Architecture Proposal)

This is just an idea for further discussion. Please see the performance tests in the previous posts.

Tuner with a differential output (e.g. R820T2 supports maximum 10 MHz bandwith), IF or near Zero IF. The management of the Tuner will be done using I2C (already tested).

The analog signal is processed by the ADC (parallel); if number of the GPIO-pins are not enough, a multiplexer can be used that transfers MSB and LSB for the 16/24-bit ADC. Then, the signal will be read from GPIO, put in memory and sent via network using Ethernet. Fast BBB GPIO can be used (2 PRUs in parallel or using a multiplexer).

Some signal processing could/must be done on the BBB but it is also necessary that the signal can be transferred unchanged via network. Moreover, it is important, that there is no sample lost. 16 bit at 5…10 MSPS is around 90 Mbit/s. May be it is possible to connect an Ethernet or USB3 to PRU GPIOs (the question is still open).

The synchronisation/time stamping of multiple receivers can be done using the Clock/Expansion Card.